Multichannel Metal Oxide Semiconductor (MOS) Transistors

ABSTRACT

Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

CLAIM FOR PRIORITY RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.10/797,463, filed Mar. 10, 2004, which claims priority from KoreanPatent Application No. 2003-30883, filed May 15, 2003, the disclosuresof which are hereby incorporated herein by reference as if set forth intheir entirety.

FIELD OF THE INVENTION

The present invention relates to integrated circuit devices and methodsof fabricating the same and, more specifically, to metal oxidesemiconductor (MOS) transistors and methods of fabricating the same.

BACKGROUND OF THE INVENTION

As integrated circuit devices become more highly integrated, the overallsize of metal oxide semiconductor (MOS) transistors have become smallerand channel lengths of the MOS transistors have also been reduced.Accordingly, short channel MOS transistors may experience apunch-through phenomenon that may cause large leakage currents betweensource and drain regions of the transistor. In addition, source anddrain junction capacitances and gate capacitances may also increase.Thus, it may be difficult to provide high performance, low powerintegrated circuit devices.

To address the problems with MOS transistors discussed above, silicon oninsulator (SOI) technology using a SOI substrate has been introduced. ASOI substrate typically includes a supporting substrate, an insulatinglayer on the supporting substrate and a silicon layer on the insulatinglayer. SOI devices may provide low junction leakage currents, reductionin frequency of punch-through, low operation voltage and high efficiencyin device isolation. However, heat generated from SOI devices duringoperation may not be efficiently conducted to the supporting substratedue to the insulating layer between the supporting substrate and thesilicon layer. Accordingly, temperatures of SOI devices may increase andthereby degrade the overall characteristics of the device. Furthermore,SOI devices may experience a floating body effect that may cause aparasitic bipolar transistor action and complex manufacturing techniquesmay be used to remove the floating body effect. Accordingly, improvedintegrated circuit devices and methods of fabricating integrated circuitdevices may be desired.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a unit cell of a metaloxide semiconductor (MOS) transistor, the unit cell including anintegrated circuit substrate a MOS transistor on the integrated circuitsubstrate. The MOS transistor includes a source region, a drain regionand a gate. The gate is positioned between the source region and thedrain region. A horizontal channel is provided between the source anddrain regions. The horizontal channel includes at least two spaced aparthorizontal channel regions.

In some embodiments of the present invention, the at least two spacedapart horizontal channel regions include an active region on theintegrated circuit substrate and at least one epitaxial pattern on theactive region and spaced apart from the active region. In certainembodiments of the present invention, the at least one epitaxial patternincludes first and second epitaxial patterns. The second epitaxialpattern may be positioned on the first epitaxial pattern and spacedapart from the first epitaxial pattern. The unit cell may furtherinclude a mask pattern on the second epitaxial pattern. The secondepitaxial pattern may be directly connected to the mask pattern.

In further embodiments of the present invention, the source and drainregions include vertical source and drain regions. The vertical sourceregion may be positioned on a first side of the horizontal channelregion and the vertical drain region may be positioned on a second sideof the horizontal channel region. The vertical drain region may also bespaced apart from the source region.

In still further embodiments of the present invention, a gate pattern isprovided on the horizontal channel and between the at least two spacedapart horizontal channel regions. A gate insulation layer may also beprovided between the gate pattern and the at least two spaced aparthorizontal channel regions channel. Source and drain electrodes may beelectrically coupled to the vertical source and drain regions,respectively. A first insulation pattern may be provided between thesource and drain electrodes and the integrated circuit substrate andbetween the gate pattern and the integrated circuit substrate.

In some embodiments of the present invention, a mask pattern may beprovided on the horizontal channel. The gate pattern may extend betweenan upper channel region of the at least two spaced apart horizontalchannel regions and the mask pattern. A second insulation pattern mayalso be provided on the horizontal channel and the vertical source anddrain regions. The second insulation pattern may define a gate openingon the horizontal channel. The gate pattern may be provided in the gateopening and the source and drain electrodes may extend through thesecond insulation pattern and be connected to the vertical source drainregions.

In further embodiments of the present invention, a third insulationpattern may be provided on the second insulation pattern and the gatepattern. The source and drain electrodes may extend through the thirdinsulation pattern and the second insulation pattern to be connected tothe vertical source and drain regions. An upper surface of the firstinsulation pattern may be higher relative to a lower surface of the gatepattern.

While the present invention is described above primarily with referencetransistors, methods of forming transistors are also provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-section of transistors according to some embodimentsof the present invention.

FIG. 1B is a cross-section taken along the line A-A′ of FIG. 1A.

FIG. 1C is a cross-section taken along the line B-B′ of FIG. 1A.

FIG. 1D is cross-section illustrating operations of transistorsaccording to some embodiments of the present invention.

FIGS. 2A through 9A are cross-sections illustrating processing steps inthe fabrication of transistors according to some embodiments of thepresent invention.

FIGS. 2B through 9B are cross-sections taken along the lines A-A′ ofFIGS. 2A through 9A illustrating processing steps in the fabrication oftransistors according to some embodiments of the present invention.

FIGS. 2C through 9C are cross-sections taken along the line B-B′ ofFIGS. 2A through 9A illustrating processing steps in the fabrication oftransistors according to some embodiments of the present invention.

FIG. 10A is a cross-section of transistors according to furtherembodiments of the present invention.

FIG. 10B is a cross-section taken along the line A-A′ of FIG. 10A oftransistors according to further embodiments of the present invention.

FIG. 10C is a cross-section taken along the line B-B′ of FIG. 10A oftransistors according to further embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein; rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. It will be further understood that when a layer is referred toas being “on” to another layer, it can be directly on the other layer orintervening layers may also be present. It will be further understoodthat when a layer is referred to as being “directly on” another layer,no intervening layers may be present. Like numbers refer to likeelements throughout.

It will be understood that although the terms first and second are usedherein to describe various layers or regions, these layers or regionsshould not be limited by these terms. These terms are only used todistinguish one layer or region from another layer or region. Thus, afirst layer or region discussed below could be termed a second layer orregion, and similarly, a second layer or region may be termed a firstlayer or region without departing from the teachings of the presentinvention.

Embodiments of the present invention will be described below withrespect to FIGS. 1A through 10C. Embodiments of the present inventionprovide unit cells of metal oxide semiconductor (MOS) transistors thatinclude a horizontal channel having at least two spaced apart channelregions. Thus, when a gate voltage is applied to a gate electrode, atleast two channels are formed at the at least two spaced aparthorizontal channel regions. MOS transistors according to someembodiments of the present invention may provide increased drivingcurrents regardless of the dimensions of the transistor due to themultiple channels corresponding to the at least two spaced aparthorizontal channel regions. Accordingly, improved MOS transistors may beprovided according to embodiments of the present invention as discussedfurther below.

Referring now to FIGS. 1A through 1C, cross-sections of transistorsaccording to embodiments of the present invention will be discussed.FIG. 1A is a cross-section of transistors according to some embodimentsof the present invention. FIG. 1B is a cross-section taken along theline A-A′ of FIG. 1A. Similarly, FIG. 1C is a cross-section taken alongthe line B-B′ of FIG. 1A. As illustrated in FIGS. 1A, 1B and 1C, a MOStransistor is provided on an integrated circuit substrate 10. Thetransistor includes a source region 52 s, a drain region 52 d and a gate34 (gate pattern). The gate 34 is provided between the source region 52s and the drain region 52 d. A horizontal channel is provided betweenthe source and drain regions 52 s and 52 d and includes at least twospaced apart horizontal channel regions 14 a and 50. The source anddrain regions 52 s and 52 d are vertical source and drain regions 52 sand 52 d. The vertical source region 52 s is provided on a first side ofthe horizontal channel regions 14 a and 50 and the vertical drain region52 d is provided on a second side of the horizontal channel regions 14 aand 50 and is spaced apart from the vertical source region 52 s. Inembodiments of the present invention illustrated in FIGS. 1A through 1C,the at least two spaced apart horizontal channel regions include anactive region 50 and first and second epitaxial patterns 14 a. Theactive region 50 may be defined by a trench 20. First and secondepitaxial patterns 14 a may be stacked sequentially on the integratedcircuit substrate and the active region 50.

It will be understood that embodiments of the present inventionillustrated in FIGS. 1A through 1C are provided for exemplary purposesonly and that embodiments of the present invention are not limited tothis configuration. For example, the horizontal channel illustrated inFIGS. 1A through 1C includes an active region 50 and first and secondepitaxial patterns 14 a, i.e., three spaced apart horizontal channelregions 50 and 14 a. However, horizontal channels according to someembodiments of the present invention may include two spaced aparthorizontal channel regions or more than three horizontal channel regionswithout departing from the scope of the present invention.

A gate pattern 34 may be provided in a gap region of the horizontalchannel regions 14 a and 50. The gate pattern may be provided on thehorizontal channel regions 14 a and 50. A gate insulation layer 32 maybe provided between the horizontal channel regions 14 a and 50 and thegate pattern 34. A mask pattern 16 a is provided on an upper surface ofthe second epitaxial pattern 14 a. In other words, the mask pattern 16 ais provided on an upper surface of the last horizontal channel region 14a in the stack of spaced apart channel regions 50 and 14 a. The maskpattern 16 a is provided between the upper surface of the secondepitaxial pattern 14 a and the gate pattern 34. The vertical source anddrain regions 52 s and 52 d are electrically coupled to a sourceelectrode 42 s and a drain electrode 42 d, respectively.

In some embodiments of the present invention, a first insulation pattern22 may be provided between the source and drain electrodes 42 s and 42 dand the integrated circuit substrate 10 to reduce leakage of a currentfrom the source and drain electrodes 42 s and 42 d into the integratedcircuit substrate 10. A second insulation pattern 30 may be provided ona surface of the integrated circuit substrate 10, including thehorizontal channel regions 14 a and 50 and the vertical source and drainregions 52 s and 52 d. The second insulation pattern 30 may define agate opening. The gate pattern 34 may be provided in the gate openingusing, for example, a damascene process. Furthermore, source and drainelectrodes 42 s and 42 d may penetrate the second insulation pattern 30,electrically coupling the source and drain electrodes 42 s and 42 d tothe source and drain regions 52 s and 52 d.

A third insulation pattern 36 may be provided on the second insulationpattern 30. In embodiments of the present invention including the thirdinsulation pattern 36, the third insulation pattern 36 may electricallyinsulate an interconnection connected to source and drain electrodes 42s and 42 d and the gate pattern 34. Furthermore, an etch stop layer 26may be provided between a lower surface of the second insulation pattern30 and the first insulation pattern 22. The etch stop layer 26 mayreduce the likelihood that the first insulation pattern 22 will be overetched during a process of forming the source and drain electrodes 42 sand 42 d. The etch stop layer 26 may also reduce the likelihood that thefirst insulation pattern 22 will be over etched during a process offorming the gate opening 28.

Referring now to FIG. 1D, a cross-section illustrating operations oftransistors according to embodiments of the present invention will bediscussed. As illustrated in FIG. 1D, a source voltage Vs and a drainvoltage Vd are applied to a source 52 s and a drain 52 d, respectively.When a gate voltage Vg is applied to a gate electrode 34 g, a channel(CH) is formed at the horizontal channel regions 14 a and 50. Inparticular, a channel is formed at the active region 50 and the firstand second epitaxial patterns 14 a. Accordingly, transistors accordingto some embodiments of the present invention, may provide increaseddriving currents regardless of the dimensions of the transistor due tothe multiple channels that are formed at the at least two spaced aparthorizontal channel regions.

Referring now to FIGS. 2A through 9C, cross-sections illustratingprocessing steps in the fabrication of transistors according toembodiments of the present invention will be discussed. FIGS. 2A through9A are cross-sectional views illustrating processing steps in thefabrication of transistors according to some embodiments of the presentinvention. FIGS. 2B through 9B are cross-sections taken along the lineA-A′ of FIGS. 2A through 9A. FIGS. 2C through 9C are cross-sectionstaken along the line B-B′ of FIGS. 2A through 9A.

Referring now to FIGS. 2A through 2C, a stacked layer 18 is formed onthe integrated circuit substrate 10. In particular, a first epitaxiallayer 12 is formed on the integrated circuit substrate. A secondepitaxial layer 14 is formed on the first epitaxial layer 12. Asillustrated in FIGS. 2B and 2C, a second set of first and secondepitaxial layers 12 and 14 may be provided on the first set of first andsecond epitaxial layers 12 and 14. It will be understood that althoughembodiments of the present invention are discussed herein as includingtwo sets of first and second epitaxial layers 12 and 14 on theintegrated circuit substrate, embodiments of the present invention arenot limited to this configuration. For example, three or more sets offirst and second epitaxial layers may be provided on the integratedcircuit substrate 10 without departing from the scope of the presentinvention. The first epitaxial layer 12 may include a material, forexample, silicon germanium, having high etch selectivity relative theintegrated circuit substrate 10, which includes, for example, silicon.The second epitaxial layer 14 may include a material similar to thematerial making up the integrated circuit substrate 10, for example,silicon. Finally, the stacked layer 18 may include a mask layer 16formed on the second epitaxial layer 14 of the upper most set of firstand second epitaxial layers 12 and 14. The second epitaxial layer orlayers 14 may be doped by implanting impurities into the stacking thesecond epitaxial layer or layers 14 after forming the stacking structure18 or during the formation of the sets of first and second epitaxiallayers 12 and 14.

Referring now to FIGS. 3A through 3C, the stacked layer 18 and theintegrated circuit substrate 10 are patterned to form a trench 20 and astacked pattern 18 a. The trench 20 defines an active region 50 of theintegrated circuit substrate 10. The stacked pattern 18 a is formed onthe active region 50. The stacked pattern 18 a includes first and secondsets of first and second epitaxial patterns 12 a and 14 a, which arealternately stacked on the active region 50. As illustrated in FIGS. 3Band 3C, the stacked pattern 18 a may further include a mask pattern 16a.

Referring now to FIGS. 4A through 4C, a first insulation pattern 22 isformed on a floor of the trench 20. The first insulation pattern 22 maybe formed by providing an insulation layer on a surface of theintegrated circuit substrate 10 and recessing the insulation layer.Accordingly, the first insulation pattern 22 is provided on theintegrated circuit substrate around the stacked pattern 18 a. The firstinsulation pattern 22 may be formed by recessing the first insulationlayer 22 until the first epitaxial pattern 12 a is exposed. Asillustrated in FIGS. 4B and 4C, a bottom surface of the active regionmay be low relative to an upper surface of the first insulation pattern22. However, in some embodiments of the present invention, a bottomsurface of the active region can be high relative to the upper surfaceof the first insulation pattern 22 without departing from the scope ofthe present invention.

Referring now to FIGS. 5A through 5C, a third epitaxial layer 24 may beformed on the surface of the stacked pattern 18 a and the exposedsurface of the integrated circuit substrate 10 using, for example, aselective epitaxial growth (SEG) process. In embodiments of the presentinvention including a mask pattern 16 a as part of the stacked pattern,the third epitaxial layer 24 may be formed on the sidewalls of thestacked pattern 18 a where the second epitaxial patterns 14 a areexposed. The third epitaxial layer 24 may include a material having anetch selectivity with respect to the first epitaxial pattern 12 a and asimilar material as the second epitaxial pattern 14 a. For example, thethird epitaxial layer 24 may include silicon.

Source and drain regions may be formed by implanting impurities into thethird epitaxial layer 24. It will be understood that the source anddrain regions may be formed in a subsequent process using, for example,conformal concentration using an oblique ion implantation. An etch stoplayer 26 is formed on a surface of the integrated circuit substrate 10.The presence of the etch stop layer 26 may reduce the likelihood of overetching the first insulation pattern 22. The etch stop layer 26 mayinclude, for example, silicon nitride.

Referring now to FIGS. 6A through 6C, a second insulation pattern 30 maybe formed on the surface of the integrated circuit substrate 10. Thesecond insulation layer 30 may be patterned to form a gate opening 28 onthe stacked pattern 18 a. In some embodiments of the present invention,the etch stop layer 26 may be patterned after the second insulationpattern 30 is patterned. Accordingly, the gate opening 28 may expose aportion of the mask pattern 16 a, the third epitaxial layer 24 and thefirst insulation pattern 22.

Referring now to FIGS. 7A through 7C, the third epitaxial layer 24 maybe removed in the gate opening 28 to expose a portion of the firstepitaxial patterns 12 a and the second epitaxial patterns 14 a. Thefirst epitaxial patterns 12 a are etched using, for example, anisotropic etch process, thereby removing the first epitaxial patterns 12a from the stacked pattern 18 a. Accordingly, the second epitaxialpatterns 14 a are provided on the active region 50 and spaced apart fromthe active region 50. Upper surfaces of the active region 50 and thesecond epitaxial patterns 14 a may provide a channel of the transistor.

A gate insulation layer 32 is formed on surface of the channel of thetransistor. In other words, the gate insulation layer 32 is formed on asurface of the active region 50 and surfaces of the second epitaxialpatterns 14 a. The gate insulation layer 32 can be formed conformallyusing, for example, a thermal process or a chemical vapor deposition(CVD) method.

Referring now to FIGS. 8A through 8C, a gate pattern 34 is provided inthe gate opening 28 by, for example, using a damascene process. Inparticular, a polysilicon layer may be formed on a surface of the secondinsulation pattern 30 and in the gate opening 28. The polysilicon layermay be planarized to form the gate pattern 34. In some embodiments ofthe present invention, the polysilicon layer may be formed in the gateopening 28 and a metal silicide layer may be formed on the resultantstructure. The metal silicide layer may be planarized to form the gatepattern 34. The gate pattern 34 is formed on the mask pattern 16 a andin the gap region between the channel regions 50 and 14 a. In furtherembodiments of the present invention, after forming a polysilicon gatepattern 34, a silicide layer may be formed by, for example, performing asilicidation process on an exposed surface of the gate pattern 34. Thechannel of the transistor can be formed on surfaces of the secondepitaxial patterns 14 a and the active region 50 opposite to the gatepattern 34.

Referring now to FIGS. 9A through 9C, a third insulation pattern 36 isformed on a surface of the integrated circuit substrate including thegate pattern 34. The third insulation pattern 36 and the etch stop layer26 may be patterned to expose the third epitaxial layer 24 to form asource contact hole 40 s on a first side of the gate pattern 34 and adrain contact hole 40 d on a second side of the gate pattern and spacedapart from the source contact hole 40 s. In some embodiments of thepresent invention, the third epitaxial layer 24 may not be doped. Thus,in these embodiments of the present invention, impurities may beimplanted through the source and drain contact holes 40 s and 40 d.

The presence of the first insulation pattern 22 on the floor of thesource and drain contact holes 40 s and 40 d may reduce the likelihoodthat the integrated circuit substrate will be over etched during theformation of the source and drain contact holes 40 s and 40 d. Aconductive layer is provided in the source and drain contact holes 40 sand 40 d to provide source and drain electrodes 42 s and 42 d (FIGS. 1Band 1C), respectively. The source and drain electrodes 42 s and 42 d areelectrically coupled to the third epitaxial layer 24.

Referring now to FIGS. 10A through 10C, cross-sections of transistorsaccording to further embodiments of the present invention will bediscussed. FIG. 10B is a cross-section taken along the line A-A′ of FIG.10A. FIG. 10C is a cross-section taken along the line B-B′ of FIG. 10A.Like reference numerals refer to like elements discussed above withrespect to FIGS. 1A through 9C and, thus, details with respect to thelike elements will not be repeated herein.

As illustrated in FIGS. 10A through 10C, a trench 20 (FIGS. 3B and 3C)is provided on the integrated circuit substrate 10. Similar to the firstembodiment, the transistor includes a horizontal channel having at leasttwo spaced apart horizontal channel regions 14 a and 50 and verticalsource and drain regions 52 s and 52 d (FIGS. 1A and 1B). Different fromembodiments of the present invention discussed above with respect toFIGS. 2A through 9C, the upper most layer of the at least two horizontalchannel regions 14 a and 50 are vertically isolated by a mask pattern 16a. The gate pattern 34 is provided in a gap region between thehorizontal channel regions 14 a and between upper most layer of thehorizontal channel region and the mask pattern 16 a. The gate pattern 34is provided on the horizontal channel regions 14 a and 50. The gateinsulation layer 32 is provided between the horizontal channel regions14 a and 50 and the gate pattern 34. However, different from embodimentsof the present invention discussed above, a channel can be formed on anupper surface of the upper most layer of the horizontal channel region.

Transistors according to some embodiments of the present inventionillustrated in FIGS. 10A through 10C may be formed using processingsteps similar to those discussed above with respect to FIGS. 2A through9C. However, in embodiments of the present invention illustrated inFIGS. 10A through 10C, the upper most layer of the stacked layer (18 ofFIGS. 2A, 2B and 2C) is formed of a material having low etch selectivityrelative to the integrated circuit substrate. As a result, the uppermost layer of the stacked pattern is removed separating the mask pattern16 a from the horizontal channel region 14 a.

As briefly discussed above with respect to FIGS. 1A through 10C,embodiments of the present invention provide a transistor having achannel including at least two channel horizontal channel regions. Highdriving currents may be used in transistors according to embodiments ofthe present invention based on the number of layers of horizontalchannel regions. Accordingly, transistors according to embodiments ofthe present invention may provide high driving currents withoutincreasing the dimensions of the transistor. Accordingly, more highlyintegrated devices may possibly be fabricated.

Furthermore, as discussed above, transistors according to embodiments ofthe present invention include vertical source and drain regions.Accordingly, the surface dimension of the source and drain regions iswide relative to conventional transistors even though the junction depthof the source and drain regions has been reduces. Therefore, theresistance of transistors according to embodiments of the presentinvention can be reduced. Finally, the presence of an etch stop layermay reduce damage caused to the integrated circuit substrate during theprocess of forming the source and drain contact holes, thus, a leakagecurrent may be reduced.

In the drawings and specification, there have been disclosed typicalpreferred embodiments of the invention and, although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation, the scope of the invention being set forthin the following claims.

1. A unit cell of a metal oxide semiconductor (MOS) transistor,comprising: an integrated circuit substrate; a MOS transistor on theintegrated circuit substrate, the MOS transistor having a verticalsource region, a vertical drain region and a plurality of gates, theplurality of gates being between the vertical source region and thevertical drain region; and a horizontal channel between the verticalsource and drain regions, the horizontal channel including at least twospaced apart horizontal channel regions, wherein widths of the pluralityof gates contacted to the at least two horizontal channel regions areidentical.
 2. The unit cell of claim 1, wherein the at least two spacedapart horizontal channel region comprise: an active region on theintegrated circuit substrate; and at least one epitaxial pattern on theactive region and spaced apart from the active region.
 3. The unit cellof claim 2, wherein the at least one epitaxial pattern comprises firstand second epitaxial patterns, the second epitaxial pattern being on thefirst epitaxial pattern and spaced apart from the first epitaxialpattern, the unit cell further comprising: a mask pattern on the secondepitaxial pattern.
 4. The unit cell of claim 3, wherein the secondepitaxial pattern is directly connected to the mask pattern.
 5. The unitcell of claim 1, wherein the source and drain regions comprise verticalsource and drain regions, the vertical source region being on a firstside of the horizontal channel region and the vertical drain regionbeing on a second side of the horizontal channel region and spaced apartfrom the vertical source region.
 6. The unit cell of claim 5, furthercomprising: a gate pattern on the horizontal channel and between the atleast two spaced apart horizontal channel regions; and a gate insulationlayer between the gate pattern and the at least two spaced aparthorizontal channel regions.
 7. The unit cell of claim 3, furthercomprising: a source electrode electrically coupled to the verticalsource region; a drain electrode electrically coupled to the verticaldrain region; and a first insulation pattern between the source anddrain electrodes and the integrated circuit substrate and between thegate pattern and the integrated circuit substrate.
 8. The unit cell ofclaim 7, wherein the gate pattern extends between an upper channelregion of the at least two spaced apart horizontal channel regions andthe mask pattern.
 9. The unit cell of claim 8, further comprising: asecond insulation pattern on the horizontal channel and the verticalsource and drain regions, wherein the second insulation pattern definesa gate opening on the horizontal channel, wherein the gate pattern isprovided in the gate opening and wherein the source and drain electrodesextend through the second insulation pattern and are connected to thevertical source drain regions.
 10. The unit cell of claim 9, furthercomprising: a third insulation pattern on the second insulation patternand the gate pattern, wherein the source and drain electrodes extendthrough the third insulation pattern and the second insulation patternand are connected to the vertical source and drain regions.
 11. The unitcell of claim 10, wherein an upper surface of the first insulationpattern is higher relative to a lower surface of the gate pattern.
 12. Aunit cell of a metal oxide semiconductor (MOS) transistor, comprising:an integrated circuit substrate including a trench and an active regionhigher than the trench, the active region protruding from the integratedcircuit substrate to function as a horizontal channel; the horizontalchannel between a vertical source region and a vertical drain region,the horizontal channel including at least two single crystallinehorizontal channel regions formed in spaced apart patterns, and furtherincluding the active region higher than the trench; a plurality of gatesbetween at least two single crystalline horizontal channel regions,wherein widths of the plurality of gates that contact the at least twosingle crystalline horizontal channel regions are substantiallyidentical; the vertical source region and the vertical drain region inother patterns at one side of the spaced apart patterns, respectively,wherein the vertical source and drain regions extend along sides of theat least two horizontal channel regions and sides of the active regionprotruding from the integrated circuit substrate; and a vertical sourceelectrode contacted to a side of the vertical source region and avertical drain electrode contacted to a side of the vertical drainregion.
 13. A transistor comprising: an integrated circuit substrateincluding a trench region to define an active region and a deviceinsulation layer on a floor of the trench region; a horizontal channelincluding a plurality of spaced apart channel layers on the activeregion, wherein widths of the plurality of spaced apart channel layersare substantially identical; a gate pattern on the horizontal channel,the gate pattern including a plurality of gates simultaneously formedbetween the plurality of spaced apart channel layers; a pair ofjunctions including a vertical source region and a vertical drain regionon the device isolation layer; and a vertical source electrode and avertical drain electrode on the device isolation layer, the verticalsource electrode contacting to a side of the source region and thevertical drain electrode contacting to a side of the drain region. 14.The transistor of claim 13, wherein an upper surface of the deviceisolation layer is lower relative to the active region.
 15. Thetransistor of claim 13, wherein the pair of junction covers sides of theactive region and sides of the plurality of spaced apart channel layers.16. The transistor of claim 13, wherein the plurality of spaced apartchannel layers are single crystalline.
 17. The transistor of claim 13,wherein the horizontal channel comprises at least one gap region, inwhich at least one gate is formed, between the plurality of spaced apartchannel layers.